523e2fb [intel/traits/load_store] Remove 16-bit loads/stores

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8f4a218 Bump to version 0.4.0

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8084a6d [intel/vector] Add 'Vector::slice_as_array' and mark things '#[inline]'

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44ba07f [intel/sse/ssse3] Implement variable byte shuffling

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aa94098 [intel/sse/sse2] Implement 'test_within()'

~bal-e pushed to ~bal-e/npsimd git

d2f6714 [intel/sse/sse2] Implement all integer max/min

~bal-e pushed to ~bal-e/npsimd git

905a8ba [intel/sse/sse2] Rewrite most tests with 'proptest'

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c5a2337 [intel/sse/sse2] Implement all signed right shifts by constant

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f0a1bd8 [intel/sse/sse2] Implement all signed right shifts by constant

~bal-e pushed to ~bal-e/npsimd git

c74f79b Implement integer ops from AVX2

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57de47c Implement AVX insert/extract intrinsics

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4741c0c Document instructions for SSE4.1

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d0cdebc Implement SSE2 aligned/unaligned stores

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018e6fb Add information to 'Cargo.toml'

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3dbc188 Bump to version 0.2.1

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