A modern VerilogA compiler focused on compact modelling
b800153 chore(internal): remove unused allow attributes
~dspom pushed to ~dspom/OpenVAF git
739320a chore(doc): add chanlog entries for 9d595e783199ffbb0e809b8987cd7da00309d59d
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3f8e8c5 chore(osdi): release version 0.1.2
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47a86b2 chore(verilogae): release beta8
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042deea fix(verilogae): fix crash when variable without assignment is retrived
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c4bf53b feat: implement type checking $limit
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56311d6 ui: improve diagnostic message for non-standard ddx lint
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678fc43 perf(osdi): if possible emit $bound_step during setup or omit fully
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ac3f27e feat(osdi): add proper support for $abstime and $bound_step
~dspom pushed to ~dspom/OpenVAF git
280644b chore(osdi): release version 0.1.1
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4c685b4 chore(verilogae): release v0.6.0-beta7
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