A modern VerilogA compiler focused on compact modelling

b800153 chore(internal): remove unused allow attributes

~dspom pushed to ~dspom/OpenVAF git

1 year, 2 months ago

739320a chore(doc): add chanlog entries for 9d595e783199ffbb0e809b8987cd7da00309d59d

~dspom pushed to ~dspom/OpenVAF git

1 year, 2 months ago


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OpenVAF is a Verilog-A compiler. The OpenVAF Project is not executable by itself but serves as the main component of various sub-projects such as VerilogAE and OSDIC. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A. Furthermore, the project aims to bring modern compiler construction algorithms/data structures to a field with a lack of such tooling.

Some highlights of OpenVAF include:

  • IDE aware design
  • high-quality diagnostic messages
  • linting framework (similar to rustc)
  • modular backend including data flow analysis and various state of the art compiler optimization algorithms
  • fast binary generation using LLVM
  • robust auto differentiation implementation


To build the project, simply run

cargo build

, which will build the project. The command

cargo test

will run the test cases.


The architectures of the rust-analyzer and rustc have heavily inspired the design of this compiler.

This work is free software and licensed under the GPL-3.0 license. It contains code that is derived from rustc and rust-analyzer. These projects are both licensed und the MIT license. As required a copy of the license and disclaimer can be found in copyright/LICENSE_MIT