VHDL compiler and simulator
efcdc19 Tag Docker images on releases. Fixes #1165
~nickg pushed to ~nickg/nvc git
f5b3fa1 Fix crash with conversion function and unconstrained input port
~nickg pushed to ~nickg/nvc git
3148e82 Implement FILE and LINE in Verilog preprocessor
~nickg pushed to ~nickg/nvc git
3658e51 Fix crash when nvc -i called with no arguments
~nickg pushed to ~nickg/nvc git
9a853a3 Add a simple pointer provenance tracking scheme
~nickg pushed to ~nickg/nvc git
04b833d Fix unit test failures on release build. Fixes #1170
~nickg pushed to ~nickg/nvc git
5625e80 Remove redundant windows.h include from jit-core.c
~nickg pushed to ~nickg/nvc git
cdaeb4e Fix VHPI crash with complex element constraints. Issue #1161
~nickg pushed to ~nickg/nvc git