Hi! I’m currently a PhD student in the Circuits and Systems group at Imperial College London, supervised by John Wickerson.
My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs). An implementation in the Coq theorem prover called Vericert can be found on Github.
I have also worked on random testing for FPGA synthesis tools. Verismith is a fuzzer that will randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output to the input. If these differ, the design is automatically reduced until the bug is located.
My personal dotfiles.
A formally verified high-level synthesis tool based on CompCert and written in Coq.
Simple zettelkasten mode for emacs.
Personal blog and website.
An implementation of the Calculus of Construction.
7013532 Update and fix the transformation
~ymherklotz pushed to ~ymherklotz/vericert git
d43f57e Add back changes to Abstr
~ymherklotz pushed to ~ymherklotz/vericert git
c0ef677 Merge remote-tracking branch 'origin/dev/scheduling' into dev/scheduling
~ymherklotz pushed to ~ymherklotz/vericert git
3f74c21 Merge remote-tracking branch 'origin/master'
~ymherklotz pushed to ~ymherklotz/dotfiles git
68895af Update lemmas with new update function
~ymherklotz pushed to ~ymherklotz/vericert git
21d2482 Add configuration to context
~ymherklotz pushed to ~ymherklotz/dotfiles git
9eb18ec Prioritise org-zettelkasten
~ymherklotz pushed to ~ymherklotz/emacs-zettelkasten git
5fa9480 Add new function to create custom ID
~ymherklotz pushed to ~ymherklotz/emacs-zettelkasten git
13f415f Update copyright
~ymherklotz pushed to ~ymherklotz/emacs-zettelkasten git